1. Field of the Invention
The present invention relates to flash analog to digital converters and more particularly relates to an improved bias circuit for folded cascode differential logic encoder circuits in high resolution flash A/D converters.
2. Description of the Related Art
Flash analog to digital converters (A/D) are known for use in high speed data acquisition applications. FIG. 1 is a simplified block diagram illustrating a flash A/D converter known in the prior art. In general, an input signal is applied to a network of comparator circuits 102. For an n-bit flash A/D converter, the signal is simultaneously applied to 2.sup.n -1 comparators. The output of the 2.sup.n -1 comparators 102 are applied to an encoder circuit 104 which provides n Gray code output lines. It is well known in the art of flash A/D converters that the use of Gray code encoding is preferred as this method reduces errors resulting from glitch noise, comparator metastability and bubble errors. The output of the encoder circuit 104 is then conventionally applied to a Gray code to binary converter 106 which has n-binary output lines.
FIG. 2 illustrates a known folded differential logic (FDL) circuit for Gray code encoding a six bit (n=6) flash A/D converter. In this figure, only the least significant bit (D.sub.0) is illustrated. For the output line, alternating comparators 200 are connected to differential bit lines 202, 204 in a manner such that a Q output 200a of 16 comparators connects to bit line 202 and the complementary output of these comparators 200b are connected to bit line 204. An additional 16 comparators have their Q output line 200a connected to bit line 204 with their respective complimentary output lines 200b connected to bit line 202. Bias current is supplied to lines 202, 204 through resistors 206, 208 respectively. A comparator 210 is connected to bit lines 202, 204 and changes stated in response to a differential voltage across lines 202, 204. A current sink 212 is connected from bit line 202 to circuit ground.
Each comparator sinks a current I.sub.0 in either the Q or the complimentary output depending on the logic state of the comparator. When an input voltage, V.sub.IN, is applied that is below the threshold voltage of the comparator 200, all the comparators are off and a quiescent current of 16 I.sub.0 is drawn in each of bit lines 202 and 204 through comparators 200. However, because of current sink 112, the total current drawn in bit line 202 is equal to 17I.sub.0. This provides an initial voltage differential across lines 202, 204 of -I.sub.0 R, which maintains comparator 210 in a logic state "0". When a voltage is applied that changes the state of one of the comparators 200, the current in bit line 202 drops from 17I.sub.0 to 16I.sub.0 while the current in bit line 204 increases from 16 I.sub.0 to 17 I.sub.0. The differential voltage across the comparator then becomes I.sub.0 R, which is detected by the comparator 210 which changes to a logic state "1" for line D.sub.0.
Typically, emitter coupled logic (ECL) is used for such high speed bipolar transistor logic circuits and a differential voltage (I.sub.0 R ) of about 400 millivolts is required. However, as the bias current for the six bit flash converter of FIG. 1 is 16 I.sub.0, a minimum bias voltage of 16.times.400 mV=6.4v is required. This voltage exceeds the preferred supply voltage (5.2 VDC) used in the majority logic circuits. This requires either providing an additional supply voltage to the flash A/D converter or reducing the differential voltage to a value less than 400 millivolts. However, reducing the differential voltage also reduces 10 t the signal to noise ratio (SNR) of the circuit, making it more prone to errors. Therefore, the FDL logic of FIG. 2 is limited in the total number of bits which can be implemented in this topology.
FIG. 3 illustrates a folded cascode differential logic (FCDL) circuit known in the prior art which addresses the problems associated with the FDL topology of FIG. 2. The circuit of FIG. 3 is presented in the article "Error Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter" by Ono et al., IEEE Journal of Solid-State Circuits, Vol. 32, No. 9, September 1997, pp. 1460-1464. In the circuit of FIG. 3, rather than supplying 16 to 17 I.sub.0 through the main bias resistors, Ono et al. teaches the use of a pair of constant current sources 300, 302 to supply a current of 18 I.sub.0 to each of bit lines 202, 204. Comparator 210 is then connected to lines 202, 204 through PNP transistors 304, 306 respectively. Bias resistors 308, 310 are connected to the collectors of transistors 304, 306 and to circuit ground. As with the circuit of FIG. 2, during the quiescent state, 17 I.sub.0 flows into bit line 202 and 16I.sub.0 flows into bit line 204. This allows 2 I.sub.0 to flow through transistor 304 and resistor 308 and I.sub.0 to flow through transistor 306 and resistor 310. When a comparator 200 turns on, 16I.sub.0 then flows in bit line 202 and 17 I.sub.0 flows into line 204. In this state, I.sub.0 flows through resistor 308 and 2.multidot.I.sub.0 flows through resistor 310 thereby creating a differential voltage that activates the comparator 210.
In the circuit of FIG. 3, only I.sub.0 to 2 I.sub.0 flows through the bias resistors 308, 310, thus avoiding the voltage problem associated with the FDL circuit of FIG. 2. However, the current sources 300, 302 are generally formed with PNP transistors or PMOS transistors. For high operating speeds (i.e., f&gt;1 GHz) I.sub.0 is generally on the order of several hundred micro amperes (.mu.A), thereby requiring current sources 300, 302 to supply up to around 10 mA. However, the transconductance of PMOS transistors is generally insufficient to provide such a high drive current and may take up large area. In bipolar technologies, PNP transistors with enough .beta. (current gain) are not generally available for this application either.
In the circuit of FIGS. 2, bit lines 202, 204 have a significant stray capacitance 214 associated therewith resulting from the large number of attached comparators 200. As the voltage on bit lines 202, 204 must change to indicate a change in logic state, this parasitic capacitance 214 adversely affects the slew rate of the device. As the resolution of the A/D is increased by one bit, the number of required comparators doubles. Therefore, the parasitic capacitance 214 quickly grows with increased resolution, thus diminishing the operating speed of high resolution devices.
Accordingly, an improved bias circuit is required for high resolution, high speed flash A/D converters. Such a bias circuit should allow operation of the flash A/D converter at conventional operating supply voltages and also reduce the slew rate effects of the parasitic capacitance on the bit lines.